Reproducible SoC
Choose a friendly FPGA board, synthesize an open RISC-V system, and make one-command builds boringly reliable.
3DVR Compute · RISC-V
Project seed · FPGA firstA small, fully open RISC-V SoC project designed to be understandable end-to-end, reproducible by other builders, and useful long before we ever manufacture silicon.
First system
Keep the architecture boring enough to understand, then make each layer better in public.
Roadmap
The project should remain useful at every stage instead of waiting years for a custom chip.
Choose a friendly FPGA board, synthesize an open RISC-V system, and make one-command builds boringly reliable.
Bring up serial, storage, networking, and enough Linux support to use the machine for actual computing.
Experiment with a small documented accelerator interface instead of depending forever on proprietary GPU stacks.
Where it leads
This project can eventually become an open compute module for 3DVR hardware. The near-term goal is learning and reproducibility; the long-term goal is a stack we could confidently put inside a Balthazar-style laptop.
Open hardware
RTL, FPGA bring-up, Linux, compilers, tinygrad, boards, documentation—small contributions are enough to move the project forward.